1) Technical Field of the Invention
The present invention relates to a semiconductor device, and in particular, to the semiconductor device that can reduce its wire inductance within a resin package.
2) Description of Related Arts
In the power semiconductor device such as a power module manufactured by a conventional technique, power chips such as an Insulated Gate Bipolar Transistor (IGBT) chip and a Free Wheel Diode (FWD) chip are mounted via a conductive adhesive layer such as a solder layer onto an insulating substrate having a wire patterned layer, which are housed in a hollow resin casing.
The power chips each include surface electrodes (e.g., an emitter electrode of the IGBT chip and an anode electrode of the FWD chip), which are electrically connected via a conductive wire and the wire patterned layer with one of main terminals. Also, the power chips each include reverse electrodes (i.e., a collector electrode of the IGBT chip and a cathode electrode of the FWD chip), which are electrically connected via a conductive wire and the wire patterned layer with the other one of main terminals. Further, a control electrode such as a gate electrode of the IGBT chip is electrically connected via a conductive wire with a control terminal. Those main terminals and the control terminal are designed to extend outside beyond the casing for electrical connection with an external circuitry. As above, the IGBT chip and the FWD chip are reversely connected in parallel to construct an inverter circuitry.
The main terminals and the control terminal are supported by the resin casing and electrically connected with the wire patterned layers. Also, the conductive wires and the wire patterned layers between the main/control terminals and the chip electrodes (surface/reverse/control electrodes) are likely to be rather redundant in accordance with configuration and structure of the hollow resin casing and the wire patterned layer as well as with arrangement of the power chips. Thus, according to the conventional power module, the wire inductance of the conductive wire and the wire patterned layer tend to be more substantial as the structure thereof is more complicated.
The greater inductance of the conductive wire and the wire patterned layer causes greater surge voltage to be applied on the power chip such as the IGBT chip. This increases energy loss during switching operation of the IGBT chip, and once the surge voltage exceeding the withstanding voltage of the IGBT chip is applied, the IGBT chip may be severely damaged by the surge voltage.
Further, as the conductive wire for electrical connection between the control terminal and the control electrode of the IGBT chip is lengthier, the IGBT is more susceptible to electromagnetic noise emitted from the outside, which may cause improper or erroneous switching operation of the IGBT chip.
Moreover, the power module often includes a plurality of inverter circuitries connected in parallel, each of which has the IGBT chip reversely connected with the FWD chip in parallel, and each of the conductive wires may have wiring length different from others. This may cause deviation (variation) of ON-switch timing of the inverter circuitries, thereby to cause unbalance in operation current running through each of the IGBT chips connected in parallel. Excessive current running through one of the IGBT chips may cause fatal damage on that chip.
Therefore, it is desired that the wiring length of each of the conductive wires and wire patterned layers for one inverter circuitry is minimized and equalized to those for the other inverter circuitries.
A Japanese Patent Application JPA 9-321216 (referred to as “Reference 1” herein) discloses a power semiconductor device capable of reducing the inductance thereof, which includes nuts soldered on a base conductive layer and a lead terminal layer within a resin casing, as illustrated in FIG. 2 of Reference 1. Those nuts perform a function serving as external lead terminals.
Also, another Japanese Patent Application JPA 9-283681 (referred to as “Reference 2” herein) discloses a semiconductor device having a resin package formed by a transfer-mold injection of thermosetting resin, on which top surface external lead terminals are provided. The semiconductor device shown in FIG. 2 of Reference 2 includes an external terminal plate having the bottom end connected with the internal wiring plate and the top end soldered with a nut that is connected with an external circuitry. The nut is assembled to have an exposed surface flush with the top surface of the resin package 8.
According to Reference 1, although the nuts are supported by a hollow resin casing and a solder layer on the lead terminal layer, the hollow resin casing is filled up with soft gel resin so that the nuts are secured with insufficient mechanical strength. Therefore, there is a drawback that the torque on the nut, which is generated while fastening the nut shaft into the nut, readily breaks the connection between the nut and the lead terminal layer.
Also, the semiconductor device of Reference 2 has another problem that when the resin package is formed by transfer-mold injection of the thermosetting resin, the substantial time is required for hardening the thermosetting resin. This causes the fluidic thermosetting resin to get in a small gap between the nut and the mold, so that a resin burr is formed on the top surface of the nut, which may block good electrical connection between the nut and the external circuitry, thereby reducing the production efficiency of the semiconductor device.
Further, the external terminal plate electrically connected with the internal wiring plate has considerable inductance which limits reduction of the total inductance of the semiconductor device.
The present invention is to address the above-described drawbacks and to provide a reliable semiconductor device, which can reduce the wiring inductance between the main terminal and the semiconductor chip, and improve the mechanical strength of the main terminal.